Just posted a new article on fundamentals of memory models in the context of multi-threading. It covers 3 basic properties: Atomicity, Visibility and Ordering, along with some compiler-related and high-level languages aspects:
http://www.1024cores.net/home/lock-free-algorithms/so-what-is-a-memory-model-and-how-to-cook-it
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Thanks for providing a good overview of the issues for memory consistency models. By the way, it's chapter 8 (not 7) in volume 3A of the Intel manuals.
ReplyDeleteYou said that SPARC as 8 memory models. I thought it was 16, since there are 4 flag bits controlling the memory model. Or are some of the combinations not supported or hopelessly silly?
Thank you, Arch.
ReplyDeleteI will fix chapter number for the Intel manual.
As for SPARC, I actually meant a chapter number - chapter 8 "memory models" :)
AFAIK, for SPARC in *practice* only 1 fence type is a no-op, the same as for Intel, membar #StoreLoad. That is, you can theoretically setup a processor in RMO mode, but real implementations are all still TSO.
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